1. Field of the Invention
This invention relates to addressing methods in computers, and more particularly, to an address-translation method and system used in conjunction with a central processing unit (CPU), such as the Intel X-86 family of microprocessors, for translating (mapping) effective addresses (EA), which are also referred to as logic addresses, into physical addresses (PA) that are used to gain access to physical locations in the memory.
2. Description of Related Art
In high-end computer systems, such as the X-86 microprocessor based personal computers, the provision of the virtual memory capability allows the microprocessor to use the main memory as though it has an expanded, limitless capacity, such that the microprocessor can execute very large programs. With virtual memory, the programmer can have a limitless memory space to use from a memory unit of a fixed size. An efficient virtual memory addressing scheme is therefore a primary research effort in the computer industry.
In X-86 based computers, the access to the virtual memory is through the use of the so-called effective addresses (EA) that are either explicitly or implicitly stated in object codes. The physical addresses (PA) that are used to gain access to the physical locations in the main memory are obtained by mapping the effective addresses in prearranged manners. In general, the mapping of the effective addresses to the physical addresses is a complex procedure that takes much time to complete.
To speed up the mapping, a conventional scheme is to use a high-speed memory unit in the microprocessor called Translation Lookaside Buffer (TLB) to carry out the address-translation process. The TLB is a specifically designed cache memory that can output the corresponding physical address of an effective address when the effective address is input thereinto. The physical addresses are determined by comparing the current linear address (LA) with prestored data in a so-called tag storage unit in the TLB. The tag storage unit is part of a content-addressable memory (CAM).
FIG. 1 is a schematic diagram of a conventional address-translation system for use on an X-86 based computer to translate effective addresses into physical addresses. This address-translation system includes an effective-address generator 10, a segment-descriptor cache memory 11, and a Translation Lookaside Buffer (TLB) 12. Further, the translation lookaside buffer 12 includes a tag storage unit 13 and a data storage unit 14 which are both built on a content-addressable memory (CAM).
The effective-address generator 10 can generate an output 32-bit effective address (EA) by summing up a base, a displacement, and an index and then multiplying the sum by a scaling factor. At the same time, the segment-descriptor cache memory 11 receives a selector address (SA) and generates a corresponding segment base (SB) which is also a 32-bit value. The effective address (EA) from the effective-address generator 10 and the segment base (SB) from the segment-descriptor cache memory 11 are then summed up to thereby obtain a linear address (LA).
The linear address (LA) is also a 32-bit value whose low-order bits 0-11 represent a segment address and whose high-order bits 12-32 represent a page address. The page address is transferred to the tag storage unit 13 in the TLB 12 where it is compared with a set of prestored linear address values LA' in the tag storage unit 13. If there is a match, the tag storage unit 13 outputs and transfers a HIT signal to the data storage unit 14 to fetch a corresponding page base (PB) from the same. The page base (PB) is a 20-bit value, which is then combined with the low-order 12-bit portion of linear address (LA) to thereby obtain a 32-bit value which serves as the desired physical address (PA).
One drawback to the foregoing address-translation system, however, is that, since the determination of the physical address (PA) requires the steps of first obtaining effective address (EA) and the linear address (LA), the computation time is quite lengthy. Moreover, since the data stored in the tag storage unit 13 are linear addresses LA' that are compared in a sequential manner, it will cause a critical path in the computation process that degrades the performance of the computer system.
FIG. 2 is a schematic diagram of another conventional address-translation system for use on an X-86 based computer to translate effective addresses into physical addresses. As shown, this address-translation system includes an effective-address generator 20, a segment-descriptor cache memory 21, a TLB 22, a translation lookaside invalid controller 23, an adder 24, and a bit combinator 26. Further, the TLB 22 includes a tag storage unit 27 and a data storage unit 28.
The effective-address generator 20 can generate a 32-bit effective address (EA). The high-order bits 12-31 of the effective address (EA), designated by EAH, are transferred to the TLB 22. A 4-bit selector address (SA) from the microcode is input to the segment-descriptor cache memory 21 which can correspondingly generate a 32-bit segment base (SB). The effective address (EA) from the effective-address generator 20 and the segment base (SB) from the segment-descriptor cache memory 21 are then summed up at the adder 24 to thereby obtain a 32-bit linear address (LA) whose low-order bits 0-11, designated by PAL, are to be used as the low-order 12 bits of the physical address (PA). At the same time, the translation lookaside invalid controller 23 outputs and transfers an invalid signal IV to the TLB 22.
In the TLB 22, the EAH value is compared with a set of prestored values EAH' in the tag storage unit 27. If there is a match, the tag storage unit 27 generates and transfers a HIT signal to the data storage unit 28. In response to the HIT signal, the data storage unit 28 outputs a corresponding page base (PB) which is a 20-bit value, represented by PAH, that is to be used as the high-order 20 bits of the physical address (PA). Subsequently, the 20-bit PAH value from the data storage unit 28 and the 12-bit PAL from the adder 24 are combined at the bit combinator 26 to thereby obtain a 32-bit value which serves as the desired physical address (PA).
One drawback to the foregoing address-translation system of FIG. 2, however, is that, since it lacks the step of comparing segment bases (SB) in the TLB 22, in the event that the segment base is changed, an action of invalidation must be imposed on all of the bits in the TLB 22. This will result in a very low hit ratio.